Draw a circuit diagram for a 2-way set associative cache that can be indexed by bytes HAVING 8 BLOCK

Draw a circuit diagram for a 2-way set associative cache that can be indexed by bytes which has 8 blocks with a block size of 8-bytes. Show the tag-match logic and the output byte select mux. Also, assume that it is a 32-bit machine and show the number of bits of the address which goes to each multiplexer and tag-comparator.
Ahmed_Shehzad
Asked Mar 08, 2017

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